Broadband modulation pll, and modulation factor adjustment method thereof

ABSTRACT

A problem of the present invention is to provide a wide band modulation PLL having good modulation accuracy at low cost. With respect to a PLL having a VCO ( 21 ), a frequency divider ( 22 ), a phase comparator ( 23 ), a charge pump ( 24 ) and a loop filter ( 25 ), the VCO ( 21 ) and a frequency dividing ratio of the frequency divider ( 22 ) are controlled to perform modulation. The VCO ( 21 ) has two control terminals for PLL and modulation, and a control signal generation part ( 28 ) generates a control voltage V tm  of the VCO ( 21 ) based on phase modulation data and an input voltage V tl  to the control terminal for PLL. At the time of adjusting a modulation factor, the control voltage V tm  to the control terminal for modulation of the VCO ( 21 ) is controlled and also the input voltage V tl  is measured and a modulation sensitivity of a frequency of the VCO ( 21 ) to V tm  is calculated and a modulation factor of the phase modulation data is adjusted based on the modulation sensitivity obtained.

TECHNICAL FIELD

The present invention relates to a wide band modulation PLL capable ofgenerating and outputting an RF (Radio Frequency) modulation signalmodulated by a modulation signal having a bandwidth wider than abandwidth of a PLL, and a modulation factor adjustment method thereof.

BACKGROUND ART

Generally, a PLL (Phase Locked Loop) modulation circuit requires lowcost, low power consumption, good noise characteristics, and modulationaccuracy. When modulation is performed in the PLL, it is desirable towiden a frequency bandwidth of the PLL (PLL band) than a frequencybandwidth of a modulation signal (modulation band) in order to improvethe modulation accuracy.

However, widening the PLL bandwidth causes degradation in the noisecharacteristics. Thus, a technique of two-point modulation in which aPLL bandwidth is set at a value narrower than a modulation bandwidth andmodulation within a PLL band and modulation without the PLL band areperformed at two different points has been devised (for example, seePatent Reference 1).

FIG. 10 is a schematic configuration diagram showing a conventional wideband modulation PLL. As shown in FIG. 10, the conventional wide bandmodulation PLL includes a PLL having a voltage controlled oscillator(hereinafter VCO) 1 in which an oscillation frequency changes accordingto a voltage of a control voltage terminal (Vt), a frequency divider 2for dividing a frequency of an RF modulation signal outputted from theVCO 1, a phase comparator 3 for comparing phases of a reference signaland an output signal of the frequency divider 2 and outputting a signalaccording to a phase difference and a loop filter 4 for averaging anoutput signal of the phase comparator, a modulation sensitivity table 7for outputting a modulation signal based on modulation data, a D/Aconverter 10 for converting an output signal of the modulationsensitivity table 7 into an analog voltage while adjusting a gainaccording to a gain control signal from a control part 6, a delta andsigma modulator 9 in which delta and sigma modulation of a signalobtained by adding channel selection information to the output signalfrom the modulation sensitivity table 7 is performed and the signal isoutputted to the frequency divider 2 as a frequency dividing ratio, andan A/D converter 11 for converting a voltage value of Vt into a digitalvalue and outputting the value to the control part 6.

FIG. 11 is a diagram showing a frequency characteristic for descriptionof an action of a wide band modulation PLL. Here, a transfer function ofthe PLL is set at H(s) (where s=jω). H(s) has a low-pass characteristicas shown in FIG. 11. A low-pass filter of a transfer function H(s) isapplied to a modulation signal added to a frequency dividing ratio setin the frequency divider 2. On the other hand, a high-pass filter of atransfer function 1-H(s) as shown in FIG. 11 is applied to a modulationsignal added to the control voltage terminal (Vt) of the VCO 1.

Since these two modulation components are added in the control voltageterminal of the VCO 1, the modulation signal is multiplied by acharacteristic shown by a broken line of FIG. 11 equivalently, that is,1 and is given to the VCO 1. As a result of that, an RF modulationsignal with a wide band ranging to the outside of a PLL band can beoutputted from the VCO 1.

By the way, amplitude of a modulation signal inputted to the controlvoltage terminal of the VCO 1 is converted into a frequency shift of anRF modulation signal outputted from the VCO 1. The conversion gain iscalled a modulation sensitivity and generally, a unit of the modulationsensitivity is [Hz/V].

Amplitude of a signal outputted from the D/A converter 10 must matchwith the modulation sensitivity of the VCO 1. That is because when thesematching is not achieved, the transfer function 1-H(s) is multiplied bythe amount of deviation (where a times) and a characteristic combinedwith H(s) shown by a broken line is not flat with respect to thefrequency as shown in FIG. 12. This becomes a factor in degradingmodulation accuracy.

FIG. 13 is a diagram showing one example of a characteristicrepresenting a change in an output signal frequency versus a controlvoltage of a general VCO. A modulation sensitivity is represented by aslope of a curve of this characteristic of frequency versus voltage. Asshown in FIG. 13, the modulation sensitivity varies depending on anoscillation frequency of the VCO, so that it is necessary to changeamplitude of a modulation signal inputted to the control voltageterminal of the VCO according to the oscillation frequency of the VCO inorder to obtain the same frequency shift modulation signal at adifferent oscillation frequency of the VCO.

FIG. 14 is a diagram showing a characteristic of a modulationsensitivity versus an oscillation frequency of a general VCO. It isapparent from the same diagram that the modulation sensitivity changesdepending on the oscillation frequency.

Here, one example of the case that it is necessary to change a controlvoltage resulting from the fact that the modulation sensitivity variesdepending on the oscillation frequency of the VCO will be described. Itis assumed that a modulation sensitivity at a frequency of 2 GHz of theVCO 1 is 100 MHz/V and the maximum frequency shift of a modulationsignal is 5 MHz. In this case, it is necessary to input a signal withthe maximum amplitude of 50 mV to Vt. However, it is assumed that amodulation sensitivity becomes 80 MHz/V at the time when a frequency ofthe VCO 1 is 2.1 GHz. In this case, it is necessary to input a signalwith the maximum amplitude of 62.5 mV to Vt. That is, the need to changeamplitude of an output signal of the D/A converter 10 by the frequencyof the VCO 1 arises.

Incidentally, a modulation sensitivity for a modulation componentincluded in a frequency dividing ratio set in the frequency divider 2becomes a frequency of a reference signal and does not change withrespect to the frequency of the VCO 1. For example, description will bemade using the case of assuming that a frequency of the VCO 1 is 2 GHzand a frequency of a reference signal is 1 MHz and the maximum frequencyshift of a modulation signal is 5 MHz as an example. In this case, achange range of the maximum frequency dividing ratio becomes 5.Therefore, in this calculation, the frequency of the VCO 1 isirrelevant.

In the case of FIG. 10, by having a characteristic of a modulationsensitivity versus a frequency as the modulation sensitivity table 7 andcalculating the amount of variation of a control voltage at the timewhen a channel frequency changes, the modulation sensitivity iscorrected and a gain of the D/A converter is adjusted.

Here, FIG. 15 is one example of a principle diagram of a VCO. The VCO 1is constructed of an inductor L, a capacitor C, a variable capacitancediode C_(v) in which capacitance varies depending on a voltage value ofa control voltage Vt and an active element 100, and an oscillationfrequency f_(VCO) is determined by a mathematical formula 1.$\begin{matrix}{f_{VCO} = \frac{1}{2\pi\sqrt{L\left( {C + C_{v}} \right)}}} & \text{〈Mathematical~~formula~~1〉}\end{matrix}$

When such a VCO is integrated into an LSI, values of elements such asthe inductor L, the capacitor C and the variable capacitance diode C_(V)vary depending on manufacturing variations. Because of this,characteristics of a modulation sensitivity versus an oscillationfrequency of the VCO vary in the respective LSIs.

However, in the conventional wide band modulation PLL, it is necessaryto prepare modulation sensitivity tables for characteristics ofmodulation sensitivities every LSI resulting from variations in thevalues of these elements. That is, it is necessary to separately measurethe tables of the modulation sensitivity versus the frequency every LSIand write and hold the tables into memory etc.

In order to prepare the modulation sensitivity tables, it is necessaryto measure the modulation sensitivities versus the frequencies of allthe channels used and as a result of that, frequency switching of thePLL is performed by the number of measurement points. Therefore, therewere circumstances in which a lot of time is taken and manufacturingcost is increased and also the amount of memory is large and cost of theLSI is also increased.

Further, a modulation sensitivity is corrected when a channel frequencyis switched, but there were also circumstances in which variations inthe modulation sensitivity because of subsequent environmentalvariations cannot be corrected and it is difficult to well maintainmodulation accuracy.

(Patent Reference 1) U.S. Pat. No. 6,211,747

DISCLOSURE OF THE INVENTION

The present invention is implemented to solve the conventional problems,and an object of the invention is to provide a wide band modulation PLLhaving good modulation accuracy at low cost.

A wide band modulation PLL of the present invention comprises a PLL partincluding a voltage controlled oscillator, a frequency divider fordividing a frequency of an output signal of the voltage controlledoscillator, a phase comparator for outputting a signal according to aphase difference between a reference signal and an output signal of thefrequency divider, and a loop filter for averaging an output of thephase comparator and outputting the output to the voltage controlledoscillator, a first modulation input part for inputting and modulating afirst modulation signal to the voltage controlled oscillator based onmodulation data inputted, and a second modulation input part forinputting a second modulation signal to a position different from thevoltage controlled oscillator of the PLL part based on the modulationdata, and the voltage controlled oscillator has a first control terminalto which the first modulation signal is inputted and a second controlterminal to which a signal based on the second modulation signal isinputted, and the first modulation input part has a modulationsensitivity calculation unit for calculating a first modulationsensitivity in the first control terminal and a modulation factoradjustment unit for adjusting a modulation factor of the modulation databased on the first modulation sensitivity calculated and outputting thefirst modulation signal.

By this configuration, the need for a lookup table every each channel iseliminated, so that a wide band modulation PLL system having goodmodulation accuracy can be provided at low cost.

Also, in a wide band modulation PLL of the present invention, themodulation sensitivity calculation unit has a modulation sensitivitycalculation part for measuring a signal inputted to the second controlterminal and calculating a second modulation sensitivity in the secondcontrol terminal and also measuring a value indicating a ratio betweenthe second modulation sensitivity and the first modulation sensitivityand calculating the first modulation sensitivity based on the secondmodulation sensitivity calculated.

By this configuration, the need for a lookup table every each channel iseliminated, so that a wide band modulation PLL system having goodmodulation accuracy can be provided at low cost.

Further, in a wide band modulation PLL of the present invention, thefirst modulation input part has an A/D converter for making digitalconversion of a signal inputted to the second control terminal of thevoltage controlled oscillator, the modulation sensitivity calculationunit, the modulation factor adjustment unit, and a D/A converter formaking analog conversion of an output of the modulation factoradjustment unit and outputting the output to the first control terminal.

By this configuration, the need for a lookup table every each channel iseliminated, so that a wide band modulation PLL system having goodmodulation accuracy can be provided at low cost.

Also, in the present invention, the first modulation input partcomprises an A/D converter for making digital conversion of a signalinputted to the second control terminal of the voltage controlledoscillator, the modulation sensitivity calculation unit and themodulation factor adjustment unit, and the modulation factor adjustmentunit outputs a digital signal to the first control terminal, and thevoltage controlled oscillator changes a frequency according to thedigital signal inputted to the first control terminal.

By this configuration, a wide band modulation PLL system with smallsize, low cost and low power consumption can be provided.

Further, in a wide band modulation PLL of the present invention, thesecond modulation input part has a frequency dividing ratio generationunit for controlling a frequency dividing ratio of the frequency dividerbased on carrier frequency data and the modulation data.

By this configuration, the need for a lookup table every each channel iseliminated, so that a wide band modulation PLL system having goodmodulation accuracy can be provided at low cost.

Also, in a wide band modulation PLL of the present invention, the secondmodulation input part has a direct digital synthesizer for generating amodulation signal based on carrier frequency data and the modulationdata and outputting the signal to the phase comparator.

By this configuration, a wide band modulation PLL system with smallsize, low cost and low power consumption can be provided.

Further, in a wide band modulation PLL of the present invention, thefirst modulation input part calculates the first modulation sensitivityand adjusting a modulation factor and outputs the first modulationsignal at the time of starting the wide band modulation PLL and everypredetermined period after the start.

By this configuration, modulation accuracy which is always good andstable with respect to environmental variations caused by temperaturevariations or power source voltage variations, etc. can be provided.

Also, the present invention provides a wireless terminal apparatuscomprising the wide band modulation PLL.

By this configuration, good modulation accuracy can be provided at lowcost.

A modulation factor adjustment method of a wide band modulation PLL ofthe present invention is a modulation factor adjustment method of a wideband modulation PLL comprising a PLL part including a voltage controlledoscillator, a frequency divider for dividing a frequency of an outputsignal of the voltage controlled oscillator, a phase comparator foroutputting a signal according to a phase difference between a referencesignal and an output signal of the frequency divider, and a loop filterfor averaging an output of the phase comparator and outputting theoutput to the voltage controlled oscillator, and the method comprisesthe steps of inputting and modulating a first modulation signal to afirst control terminal of the voltage controlled oscillator, inputtingcarrier frequency data and inputting a second modulation signal to aposition different from the voltage controlled oscillator of the PLLpart based on the PLL, calculating a first modulation sensitivity in thefirst control terminal of the voltage controlled oscillator, andadjusting a modulation factor of the first modulation signal based onthe first modulation sensitivity calculated.

By this method, the need for a lookup table every each channel iseliminated in adjusting a modulation factor, so that a wide bandmodulation PLL system having good modulation accuracy can be provided atlow cost.

Also, in a modulation factor adjustment method of the present invention,the step of calculating the first modulation sensitivity comprises thesteps of measuring an input voltage inputted to a second controlterminal different from the first control terminal of the voltagecontrolled oscillator based on the second modulation signal, calculatinga second modulation sensitivity in the second control terminal, andmeasuring a value indicating a ratio between the second modulationsensitivity and the first modulation sensitivity and calculating thefirst modulation sensitivity based on the second modulation sensitivitycalculated.

By this method, the need for a lookup table every each channel iseliminated in adjusting a modulation factor, so that a wide bandmodulation PLL system having good modulation accuracy can be provided atlow cost.

According to the present invention, a wide band modulation PLL havinggood modulation accuracy can be provided at low cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic configuration diagram showing a wide bandmodulation PLL for describing a first embodiment of the presentinvention;

FIG. 2 is a schematic configuration diagram showing a control signalgeneration part of the wide band modulation PLL according to the firstembodiment;

FIG. 3 is a principle diagram of a VCO of the wide band modulation PLLaccording to the first embodiment;

FIG. 4 is a diagram showing characteristics of oscillation frequenciesversus voltages respectively applied to a control voltage terminal forPLL and a control voltage terminal for modulation of a VCO;

FIG. 5 is a diagram showing a timing chart of modulation factoradjustment;

FIG. 6 is a schematic configuration diagram showing a wide bandmodulation PLL for describing a second embodiment of the presentinvention;

FIG. 7 is a schematic configuration diagram showing a wide bandmodulation PLL for describing a third embodiment of the presentinvention;

FIG. 8 is a principle diagram showing one example of a VCO used in thewide band modulation PLL according to the third embodiment;

FIG. 9 is a wide band modulation PLL for describing a fourth embodimentof the present invention;

FIG. 10 is a schematic configuration diagram showing a conventional wideband modulation PLL;

FIG. 11 is a diagram showing a frequency characteristic for descriptionof an action of a wide band modulation PLL;

FIG. 12 is a diagram showing a frequency characteristic for descriptionof an action of the wide band modulation PLL;

FIG. 13 is a diagram showing one example of a characteristicrepresenting a change in an output signal frequency versus a controlvoltage of a general VCO;

FIG. 14 is a diagram showing a characteristic of a modulationsensitivity versus an oscillation frequency of a general VCO; and

FIG. 15 is one example of a principle diagram of a VCO.

Incidentally, numerals 21 and 50 in the drawings denote voltagecontrolled oscillators, and numeral 22 denotes a frequency divider, andnumeral 23 denotes a phase comparator, and numeral 24 denotes a chargepump, and numeral 25 denotes a loop filter, and numeral 26 denotes afrequency dividing ratio generation part, and numeral 27 denotes an A/Dconverter, and numeral 28 denotes a control signal generation part, andnumeral 29 denotes a D/A converter, and numeral 30 denotes a measurementresult storage part, and numeral 31 denotes an operation part, andnumeral 32 denotes an operation result storage part, and numeral 33denotes a modulation factor adjustment unit, and numeral 34 denotes acalibration data generation part, and numeral 35 denotes an outputsignal control part, and numeral 40 denotes a DDS.

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment

FIG. 1 is a schematic configuration diagram showing a wide bandmodulation PLL for describing a first embodiment of the presentinvention. In FIG. 1; a wide band modulation PLL according to the firstembodiment comprises a PLL having a voltage controlled oscillator(hereinafter VCO) 21 with two control voltage terminals for PLL (inputvoltage V_(tl)) and modulation signal input (input voltage V_(tm)), afrequency divider 22 for dividing a frequency of an output signal of theVCO 21, a phase comparator 23 for comparing a phase of a referencesignal with a phase of an output signal of the frequency divider 22 andoutputting a signal according to a phase difference, a charge pump 24for converting an output signal of the phase comparator 23 into acontrol signal of the VCO 21 and a loop filter 25 for smoothing anoutput signal of the charge pump 24 and outputting a control voltageV_(tl) to the control voltage terminal for PLL of the VCO 21.

Further, the wide band modulation PLL according to the first comprises afrequency dividing ratio generation part 26 for generating a frequencydividing ratio set in the frequency divider 22 from phase modulationdata and carrier frequency data inputted from the outside, an A/Dconverter 27 connected to the loop filter 25, a control signalgeneration part 28 for adjusting a modulation factor of modulation datawhile generating a control signal to the VCO 21 based on the phasemodulation data and an output signal of the A/D converter 27, and a D/Aconverter 29 for making D/A conversion of the adjusted modulation dataand outputting a control voltage V_(tm) to the control voltage terminalfor modulation signal of the VCO 21 as an analog signal.

Next, the control signal generation part 28 will be described using FIG.2. FIG. 2 is a schematic configuration diagram showing the controlsignal generation part of the wide band modulation PLL according to thefirst embodiment. The control signal generation part 28 comprises ameasurement result storage part 30 for storing an output of the A/Dconverter 27, an operation part 31 for computing and processing a valuestored in the measurement result storage part 30, an operation resultstorage part 32 for storing a result computed and processed in theoperation part 31, a modulation factor adjustment unit 33 for adjustinga modulation factor of phase modulation data based on an operationresult stored in the operation result storage part 32, a calibrationdata generation part 34 for setting a control voltage V_(tm) inputted tothe control voltage terminal for modulation signal of the VCO 21 at thetime of measuring a modulation sensitivity based on a set value controlsignal, and an output signal control part 35 for selecting any one ofcalibration data outputted by the calibration data generation part 34and modulation data outputted by the modulation factor adjustment unit33 based on a selection control signal and outputting the data to theD/A converter 29. Here, the output signal control part 35 selects anoutput of the modulation factor adjustment unit at the time of a normalmodulation operation, and selects an output of the calibration datageneration part 34 at the time of measuring a modulation sensitivity.

Here, the carrier frequency data, the phase modulation data, the setvalue control signal, and the selection control signal are outputtedfrom a control part (not shown). Incidentally, these control signals anddata may be outputted by individual control parts or may be outputted byone control part for controlling the wide band modulation PLL. Further,when such a wide band modulation PLL is applied to a wirelesscommunication apparatus such as a wireless base station or a mobileterminal apparatus, these control signals and data may be outputted by acontrol part for controlling an action of such a wireless communicationapparatus etc.

FIG. 3 is a principle diagram of a VCO of the wide band modulation PLLaccording to the first embodiment. It comprises an inductor L, acapacitor C, a variable capacitance diode C_(vl), a variable capacitancediode C_(vm) and an active element 100, and an oscillation frequencyf_(VCO) is determined by a mathematical formula 2. $\begin{matrix}{f_{VCO} = \frac{1}{2\pi\sqrt{L\left( {C + C_{vl} + C_{vm}} \right)}}} & \text{〈Mathematical~~formula~~2〉}\end{matrix}$

Here, in the present embodiment, a frequency of the VCO 21 is controlledby changing a capacitance value of C_(vl) through control of the voltageV_(tl). As a result of this, a bias potential of V_(tm) can be fixedregardless of the frequency of the VCO 21, so that a modulationsensitivity of the VCO 21 by a change in V_(tm) can be heldsubstantially constant.

FIG. 4 is a diagram showing characteristics of oscillation frequenciesversus voltages respectively applied to a control voltage terminal forPLL and a control voltage terminal for modulation of a VCO. FIG. 4(a) isa characteristic of an oscillation frequency f_(VCO) of the VCO 21versus a voltage V_(tl) applied to the control voltage terminal for PLLand at this time, a control voltage V_(tm) for modulation is set at afixed value V_(tm0). FIG. 4(b) is a characteristic of an oscillationfrequency f_(VCO) of the VCO 21 versus a voltage V_(tm) applied to thecontrol voltage terminal for modulation and at this time, a controlvoltage V_(tl) for PLL is set at a fixed value V_(tl0). When any one ofthe control voltages V_(tl) and V_(tm) is set at a fixed value, theoscillation frequency of the VCO 21 can be changed by changing the othercontrol voltage.

Next, a method for adjusting a modulation factor in the wide bandmodulation PLL according to the present embodiment will be described. Inthe present embodiment, in the control signal generation part 28 shownin FIG. 2, a modulation sensitivity K_(m) in the control voltageterminal for modulation of the VCO 21 is calculated and a modulationfactor of modulation data is adjusted so as to compensate for an errorof a gain to a modulation factor by a frequency dividing ratio based onthis modulation sensitivity K_(m).

Here, the modulation sensitivity K_(m) in the control voltage terminalfor modulation of the VCO 21 depends on a modulation sensitivity K_(l)in the control voltage terminal for PLL, so that it is first necessaryto obtain K_(l). A method of calculation and measurement of themodulation sensitivity K_(l) in the control voltage terminal for PLL andthe modulation sensitivity K_(m) in the control voltage terminal formodulation will be described below.

First, a control voltage V_(tm) is set at a fixed value V_(tm0) by thecalibration data generation part 34 of the control signal generationpart 28. The output signal control part 35 is in a state of measuring amodulation sensitivity, therefore, the fixed value V_(tm0) of thecontrol voltage is inputted to the VCO 21 through the D/A converter 29as an output signal of the calibration data generation part 34.

In this state, carrier frequency data in which a frequency of the VCO 21is locked at f₀ is inputted to the frequency dividing ratio generationpart 26. Here, the frequency f₀ is a frequency of a channel which wantsto be used finally. When it is assumed that a reference frequency isf_(ref) and a frequency dividing ratio set in the frequency divider isN₀, N₀ is expressed by a mathematical formula 3. $\begin{matrix}{N_{0} = \frac{f_{0}}{f_{ref}}} & \text{〈Mathematical~~formula~~3〉}\end{matrix}$

When N₀ satisfying the mathematical formula 3 is inputted to thefrequency divider 22, as a result of that, f_(VCO) is locked at thefrequency f₀ (point am in FIG. 4(b)). At this time, as shown by a pointat of FIG. 4(a), a voltage applied to the control voltage terminal forPLL of the VCO 21 becomes V_(tl)=V_(tl0) and this value is convertedinto a digital value using the A/D converter 27 and V_(tl0) is stored inthe measurement result storage part 30 of the control signal generationpart 28.

Next, a carrier frequency in which a frequency of the VCO 21 is lockedat f₁ is inputted to the frequency dividing ratio generation part 26 inlike manner. In this case, when it is assumed that a frequency dividingratio set in the frequency divider is N₁, N₁ is shown by a mathematicalformula 4. $\begin{matrix}{N_{1} = \frac{f_{1}}{f_{ref}}} & \left\langle {{Mathematical}\quad{formula}\quad 4} \right\rangle\end{matrix}$

When N₁ satisfying the mathematical formula 4 is inputted to thefrequency divider 26, as a result of that, f_(VCO) is locked at thefrequency f₁. At this time, as shown by a point β_(t) of FIG. 4(a), avoltage applied to the control voltage terminal for PLL of the VCO 21becomes V_(tl)=V_(tl1) and similarly, conversion into a digital value ismade by the A/D converter 27 and V_(tl1) is stored in the measurementresult storage part 30 of the control signal generation part 28.

The operation part 31 of the control signal generation part 28calculates a modulation sensitivity K_(l) in the control voltageterminal for PLL based on a measured result. Here, the modulationsensitivity K_(l) is expressed by a mathematical formula 5.$\begin{matrix}{K_{l} = \frac{f_{1} - f_{0}}{V_{tl1} - V_{tl0}}} & \text{〈Mathematical~~formula~~5〉}\end{matrix}$

As described above, the modulation sensitivity K_(l) of the controlvoltage terminal for PLL in the vicinity of a channel frequency f₀ canbe obtained. This result is stored in the operation result storage part32 of the control signal generation part 28.

Next, a calculation method of the modulation sensitivity K_(m) in thecontrol voltage terminal for modulation of the VCO 21 will be described.First, consider a state of locking a frequency of the VCO 21 at f₀ inthe case that a voltage value of an input control voltage V_(tm) of thecontrol voltage terminal for modulation is set at V_(tm)=V_(tm0) in amanner similar to the case of obtaining the modulation sensitivityK_(l). A value of V_(tl0) which is a control voltage of input to thecontrol voltage terminal for PLL at this time is obtained in acalculation process of the modulation sensitivity K_(l) and is alreadystored in the measurement result storage part 30.

Next, a set value of the calibration data generation part 34, that is, avalue outputted from the control signal generation part 28 is changed toV_(tm)=V_(tm1). Then, as shown in FIG. 4(b), in V_(t)=V_(tl0), f_(VCO)tends to change to a frequency f₂ (tends to move from a point α_(m) to apoint δ_(m) in FIG. 4(b)). However, by a loop characteristic of the PLL,V_(tl) changes so that f_(VCO) becomes a frequency f₀ and as shown by anarrow, a characteristic of the control voltage V_(tm) versus thefrequency f_(VCO) changes and is finally locked at the frequency f₀(moves from the point δ_(m) to a point γ_(m) in FIG. 4(b)).

The control voltage V_(tl) of input to the control voltage terminal forPLL at this time is set at V_(tl2) (a point γ_(t) in FIG. 4(b)). A valuein which this V_(tl2) is converted into a digital value by the A/Dconverter 27 is stored in the measurement result storage part 30 of thecontrol signal generation part 28. At this time, a relation shown by amathematical formula 6 holds between the modulation sensitivity K_(m)and the modulation sensitivity K_(l). $\begin{matrix}{K_{m} = {\frac{V_{tm1} - V_{tm0}}{V_{tl0} - V_{tl2}} \times K_{l}}} & \text{〈Mathematical~~formula~~6〉}\end{matrix}$

Here, K_(l) is already obtained and is stored in the operation resultstorage part 32 of the control signal generation part 28 and alsoV_(vt0), V_(vt2), V_(tm0), V_(tm1) are stored in the measurement resultstorage part 30, so that the operation part 31 obtains a modulationsensitivity K_(m) of the control voltage terminal for modulation signalin the vicinity of a carrier frequency f₀ based on the mathematicalformula 6 and the obtained modulation sensitivity K_(m) is stored in theoperation result storage part 32.

By the way, the mathematical formula 6 is the conversion of amathematical formula showing a ratio between the modulation sensitivityK_(m) and the modulation sensitivity K_(l) so that the measured V_(tl0),V_(tl2), V_(tm0), V_(tm1) become factors showing the ratio between themodulation sensitivities K_(m) and K_(l). Therefore, the method forobtaining the modulation sensitivity K_(m) is, in other words, a methodfor measuring and calculating the ratio between the modulationsensitivities K_(m) and K_(l).

Based on the modulation sensitivity K_(m) obtained in this manner, themodulation factor adjustment unit 33 determines a gain to phasemodulation data. When modulation factor adjustment is completed, thewide band modulation PLL starts a normal modulation operation and theoutput signal control part 35 of the control signal generation part 28is switched so as to output an output from the modulation factoradjustment unit 33 to the D/A converter 29 by a selection controlsignal. A gain error of control signal modulation of the voltagecontrolled oscillator 21 and frequency dividing ratio modulation of thefrequency divider 22 can be compensated by controlling a voltage of theVCO 21 based on the phase modulation data in which the gain is adjustedby the modulation factor adjustment unit 33.

Such modulation factor adjustment is made, for example, every time thewide band modulation PLL is started and every time a carrier frequencyused is changed (hereinafter called initial correction). A procedure atthe time of this initial correction will be described below withreference to FIG. 5. FIG. 5 is a diagram showing a timing chart ofmodulation factor adjustment. Here, description will be made using thecase of performing modulation at a center frequency f₀ andV_(tm)=V_(tm0) as an example.

First, at time to, carrier frequency data of a frequency f₁ is inputted.At this time, the calibration data generation part 34 sets V_(tm) atV_(tm0). The PLL converges to the frequency f₁ by time t₁ and themeasurement result storage part 30 measures and stores V_(tl1) betweent₁ and t₂.

Next, at time t₂, the carrier frequency data is set at a frequency f₀and the calibration data generation part 34 sets V_(tm) at V_(tm1). Inthis state, the measurement result storage part 30 measures and storesV_(vt2). Finally, at time t₃, the calibration data generation part 34sets V_(tm) at V_(tm0) and thereby the frequency f₀ does not vary by aloop characteristic of the PLL, but V_(tl) varies from V_(vt2) toV_(tl0). In this state, the measurement result storage part 30 measuresand stores V_(tl0) and the operation part 31 calculates a modulationsensitivity K_(m) based on the mathematical formula 5 and themathematical formula 6. In this manner, by the modulation factoradjustment unit 33, a gain is set at a proper value and a normalmodulation operation is started from time t₄.

Incidentally, as described above, by using V_(tl1), V_(tl2), V_(tl0) asa concrete example of order of measuring an input voltage V_(t) to thecontrol voltage terminal for PLL of the VCO 21, at the time of startingthe normal modulation operation, setting is already made at the carrierfrequency f₀ and control voltage V_(tm0), so that the wide bandmodulation PLL can speedily shift to the normal modulation operation.However, measurement of this voltage V_(t) can be achieved in any order.

Next, a method of correction to variations in environment after initialcorrection, that is, after starting the normal modulation operation willbe described. At the time of the completion or after the completion ofinitial correction, the peak value of vibration amplitude of V_(tl) inthe control voltage terminal for PLL of the VCO 21 is stored in themeasurement result storage part 30 through the A/D converter 27. At thistime, a value of V_(tm) (DC value) is associated as V_(tm0). Then, inlike manner subsequently, the vibration amplitudes are monitored atproper time intervals. Here, the proper time intervals refer to theextent to which variations in temperature or power source voltage can bemonitored. When this peak value varies, a modulation sensitivity K_(l)in the PLL control voltage terminal changes by the varying proportionand an absolute value of the modulation sensitivity K_(l) changing fromthe modulation sensitivity K_(l) obtained by the initial correction isobtained.

On the other hand, still at proper time intervals, V_(tm) is slightlychanged from V_(tm0) to V_(tm0)′. At this time, V_(tl) slightly changesin a manner similar to the initial correction. This change amount isstored and a value of V_(tm) is again changed to V_(tm0). From themodulation sensitivity K_(l) and the proportion of this change amount ofV_(tl), a modulation sensitivity K_(m) of the side of the controlvoltage terminal for modulation is obtained in a manner similar to theinitial correction. Modulation accuracy which is always good and stablewith respect to environmental variations caused by temperaturevariations or power source voltage variations, etc. by adjusting amodulation factor based on this modulation sensitivity K_(m) can beprovided.

According to the wide band modulation PLL of such a first embodiment,the need for a lookup table every each channel is eliminated, so that awide band modulation PLL with small size, low cost and low powerconsumption can be provided. Further, it can respond to variations inenvironment at the time of actual use, for example, a normal modulationoperation or every initial operation, so that a wide band modulation PLLfor achieving modulation accuracy which is always good and stable can beprovided.

Second Embodiment

FIG. 6 is a schematic configuration diagram showing a wide bandmodulation PLL for describing a second embodiment of the presentinvention. The same numerals are attached to portions overlapping withFIG. 1 described in the first embodiment.

In FIG. 6, the wide band modulation PLL according to the secondembodiment includes a direct digital synthesizer (hereinafter DDS) 40and differs from that of the first embodiment in that a point at whichphase modulation is performed is two points of the DDS 40 and a VCO 21.

The DDS 40 is adapted for directly outputting a result of numericaloperation through a built-in D/A converter etc. and as shown in FIG. 6,based on carrier frequency data and phase modulation data, numericalcalculation can be performed to output a carrier signal and a modulationsignal. Since modulation in the DDS 40 is similar to frequency dividingratio modulation of the first embodiment, modulation factor adjustmentand calculation of a modulation sensitivity of a control voltageterminal for modulation signal can be obtained by a similar method.

However, in an output of the DDS 40, a waveform is directly generated bynumerical operation, so that a fixed frequency divider with fixing of afrequency dividing ratio can be applied as a frequency divider 2disposed in the wide band modulation PLL. The fixed frequency dividercan be constructed by connecting plural frequency dividers inlongitudinal sequence and an operating frequency decreases with a backstage further, so that power consumption can be reduced.

According to such a second embodiment of the present invention,modulation accuracy which is always good and stable with respect toenvironmental variations caused by temperature variations or powersource voltage variations, etc. can be provided. Also, the need for alookup table every each channel is eliminated, so that a wide bandmodulation PLL system with small size, low cost and low powerconsumption can be provided. Further, a fixed frequency divider can beapplied as a frequency divider, so that power consumption can bereduced.

Third Embodiment

FIG. 7 is a schematic configuration diagram showing a wide bandmodulation PLL for describing a third embodiment of the presentinvention. The same numerals are attached to portions overlapping withFIG. 1 described in the first embodiment.

In the present embodiment, a signal outputted from a control signalgeneration part 28 is inputted to a VCO 50 in a state of a digitalsignal without making D/A conversion. The VCO 50 has a switch and smallcapacitance in parallel with an LC resonator, and performs an actionsimilar to that of the VCO 21 shown in FIG. 3 by changing the totalcapacitance value by controlling this switch through the digital signal.A method of adjustment and measurement of a modulation sensitivity issimilar to that of the first embodiment.

FIG. 8 is a principle diagram showing one example of a VCO used in thewide band modulation PLL according to the third embodiment. As shown inFIG. 8, in the VCO 50, n C_(vm(1)) to C_(vm(n)) in which capacitance isvariable in binary by an input digital signal are connected in paralleland by switching each of the capacitances, modulation can be performedby the sum of these capacitances. By this configuration, the VCO 50 canbe controlled to perform modulation using digital outputs V_(tm) of thecontrol signal generation part 28.

According to such a third embodiment of the present invention,modulation accuracy which is always good and stable with respect toenvironmental variations caused by temperature variations or powersource voltage variations, etc. can be provided. Also, the need for alookup table every each channel or a D/A converter is eliminated, sothat a wide band modulation PLL system with small size, low cost and lowpower consumption can be provided.

Fourth Embodiment

FIG. 9 is a schematic configuration diagram showing a wide bandmodulation PLL for describing a fourth embodiment of the presentinvention. The same numerals are attached to portions overlapping withFIGS. 1, 6 and 7 described in the first, second and third embodiments.

As shown in FIG. 9, in the wide band modulation PLL of the presentembodiment, modulation is performed at points of a DDS 40 and a VCO 50and a digital signal is applied to a modulation signal inputted from acontrol signal generation part 28 to a modulation side control terminalof the VCO 50. A method of correction and measurement of a modulationsensitivity is similar to that of the first embodiment, and an action ofthe DDS 40 is similar to that of the second embodiment, and an action ofthe VCO 50 is similar to that of the third embodiment.

According to such a fourth embodiment of the present invention,modulation accuracy which is always good and stable with respect toenvironmental variations caused by temperature variations or powersource voltage variations, etc. can be provided. Also, the need for alookup table every each channel or a D/A converter is eliminated, sothat a wide band modulation PLL system with small size, low cost and lowpower consumption can be provided. Further, a fixed frequency dividercan be applied as a frequency divider, so that power consumption can bereduced.

The description has been made above with reference to the first tofourth embodiments, but the present invention is not limited to theseconfigurations. For example, setting of a frequency dividing ratio hasbeen made with respect to a variable frequency divider inside a loop,but a configuration in which a variable frequency divider for dividing afrequency of a reference signal and outputting the signal to a phasecomparator is disposed and setting of a frequency dividing ratio is madeby the variable frequency divider can be achieved similarly. Also, anA/D converter or a D/A converter can similarly be achieved in placesother than the places used in the description, and the boundary betweenanalog and digital may be present in any places. Also, a D/A converterin which a low-pass filter is included in the output side can beachieved similarly.

The present invention has been described in detail with reference to theparticular embodiments, but it is apparent to those skilled in the artthat various changes or modifications can be made without departing fromthe spirit and scope of the present invention.

The present application is based on Japanese Patent application No.2003-298858 filed on Aug. 22, 2003, the contents of which are herebyincorporated by reference.

INDUSTRIAL APPLICABILITY

A wide band modulation PLL of the present invention has an effectcapable of achieving good modulation accuracy at low cost, and is usefulfor a wireless communication apparatus etc. of a wireless base stationapparatus etc. or a mobile wireless device.

1. A wide band modulation PLL, comprising: a PLL part, including: avoltage controlled oscillator; a frequency divider that divides afrequency of an output signal of the voltage controlled oscillator; aphase comparator that outputs a signal based on a phase differencebetween a reference signal and the output signal of the frequencydivider; and a loop filter that outputs an output to the voltagecontrolled oscillator so as to average the output of the phasecomparator; a first modulation input part that inputs a first modulationsignal to the voltage controlled oscillator based on inputted modulationdata for modulating; and a second modulation input part that inputs asecond modulation signal to a position different from the voltagecontrolled oscillator in the PLL part based on the modulation data,wherein the voltage controlled oscillator includes a first controlterminal to which the first modulation signal is inputted and a secondcontrol terminal to which a signal based on the second modulation signalis inputted; and wherein the first modulation input part has amodulation sensitivity calculation unit that calculates a firstmodulation sensitivity in the first control terminal and a modulationfactor adjustment unit that adjusts a modulation factor of themodulation data based on the calculated first modulation sensitivity andoutputs the first modulation signal.
 2. The wide band modulation PLL asset forth in claim 1, wherein the modulation sensitivity calculationunit has a modulation sensitivity calculation part that measures asignal inputted to the second control terminal, that calculates a secondmodulation sensitivity in the second control terminal, that measures avalue indicating a ratio between the second modulation sensitivity andthe first modulation sensitivity, and that calculates the firstmodulation sensitivity based on the calculated second modulationsensitivity.
 3. The wide band modulation PLL as set forth in claim 1,wherein the first modulation input part has an A/D converter that makesdigital conversion of a signal inputted to the second control terminalof the voltage controlled oscillator, the modulation sensitivitycalculation unit, the modulation factor adjustment unit, and a D/Aconverter that makes analog conversion of an output of the modulationfactor adjustment unit and that outputs the output to the first controlterminal.
 4. The wide band modulation PLL as set forth in claim 1,wherein the first modulation input part includes an A/D converter thatmakes digital conversion of a signal inputted to the second controlterminal of the voltage controlled oscillator, the modulationsensitivity calculation unit, and the modulation factor adjustment unit;wherein the modulation factor adjustment unit outputs a digital signalto the first control terminal; and wherein the voltage controlledoscillator changes a frequency based on the digital signal inputted tothe first control terminal.
 5. The wide band modulation PLL as set forthin any claim 1, wherein the second modulation input part has a frequencydividing ratio generation unit that controls a frequency dividing ratioof the frequency divider based on carrier frequency data and themodulation data.
 6. The wide band modulation PLL as set forth in claim1, wherein the second modulation input part has a direct digitalsynthesizer that generates a modulation signal based on carrierfrequency data and the modulation data and that outputs the modulationsignal to the phase comparator.
 7. The wide band modulation PLL as setforth in claim 1, wherein the first modulation input part calculates thefirst modulation sensitivity, adjusts a modulation factor and outputsthe first modulation signal at the time of an activation of the wideband modulation PLL and every predetermined period is elapsed after theactivation.
 8. The wireless terminal apparatus incorporating the wideband modulation PLL according to any one of claims 1 through
 7. 9. Amodulation factor adjustment method of a wide band modulation PLLcomprising a PLL part including a voltage controlled oscillator, afrequency divider for dividing a frequency of an output signal of thevoltage controlled oscillator, a phase comparator for outputting asignal according to a phase difference between a reference signal and anoutput signal of the frequency divider, and a loop filter for averagingan output of the phase comparator and outputting the output to thevoltage controlled oscillator, the method comprising: inputting a firstmodulation signal to a first control terminal of the voltage controlledoscillator for modulating; inputting a second modulation signal to aposition different from the voltage controlled oscillator in the PLLpart based on the PLL by inputting carrier frequency data; calculating afirst modulation sensitivity in the first control terminal of thevoltage controlled oscillator, and adjusting a modulation factor of thefirst modulation signal based on the calculated first modulationsensitivity.
 10. The modulation factor adjustment method of a wide bandmodulation PLL as set forth in claim 9, wherein the step of calculatingthe first modulation sensitivity comprises the steps of: measuring aninput voltage inputted to a second control terminal being different fromthe first control terminal in the voltage controlled oscillator based onthe second modulation signal; second control terminal; and measuring avalue indicating a ratio between the second modulation sensitivity andthe first modulation sensitivity, and calculating the first modulationsensitivity based on the calculated second modulation sensitivity.